february 1996 nds9959 dual n-channel enhancement mode field effect transistor general description features _________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter nds9959 units v dss drain-source voltage 50 v v gss gate-source voltage 20 v i d drain current - continuous @ t a = 25c (note 1a) 2.0 a - continuous @ t a = 70c (note 1a) 1.6 - pulsed @ t a = 25 c 8 p d power dissipation for dual operation 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 40 c/w nds9959.sam these n-c hannel enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. these devices are particularly suited for low voltage applications such as dc motor control and dc/dc conversion where fast switching, low in-line power loss, and resistance to transients are needed. 2.0 a, 50v. r ds(on ) = 0.3 w @ v gs = 10v high density cell design for extremely low r ds(on) . high power and current handling capability in a widely used surface mount package. dual mosfet in surface mount package. 1 5 6 7 8 4 3 2 ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 50 v i dss zero gate voltage drain current v ds = 40 v, v gs = 0 v 2 a t j = 55c 25 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 1.5 a 0.3 w v gs = 5 v, i d = 0.6 a 0.5 i d (on) on-state drain current v gs = 10 v, v ds = 5 v 8 a g fs forward transconductance v ds = 15 v, i d = 2.0 a 1 2.7 s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz 152 250 pf c oss output capacitance 50 85 pf c rss reverse transfer capacitance 12 25 pf switching ch aracteristics (note 2) t d(on) turn - on delay time v dd = 30 v, i d = 0.6 a, v gs = 10 v, r l = 50 w , r gen = 6 w 4 40 ns t r turn - on rise time 8 70 ns t d(off) turn - off delay time 9 100 ns t f turn - off fall time 11 70 ns q g total gate charge v ds = 25 v, i d = 1.3 a, v gs = 10 v 4.3 15 nc q gs gate-source charge 1.1 nc q gd gate-drain charge 1.5 nc nds9959.sam
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics and maximum ratings i s maximum continuos drain-source diode forward current 1.8 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.25 a (note 2) 0.84 1.2 v t rr reverse recovery time v gs = 0v, i f = 1.25 a, di f /dt = 100 a/s 100 ns notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja for single device operation using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 78 o c/w when mounted on a 0.5 in 2 pad of 2oz cpper. b. 125 o c/w when mounted on a 0.02 in 2 pad of 2oz cpper. c. 135 o c/w when mounted on a 0.003 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300s, duty cycle < 2.0%. nds9959.sam 1a 1b 1c
nds9959.sam 0 1 2 3 4 5 6 7 8 0 2 4 6 8 10 12 v , drain-source voltage (v) i , drain-source current (a) 6.0 5.0 8.0 7.0 v =10v ds d 9.0 gs -50 -25 0 25 50 75 100 125 150 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t , junction temperature (c) drain-source on-resistance (ohms) j v =10v gs i = 1.5a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage (v) j i = 250a d v = v ds gs v , normalized th 0 2 4 6 8 10 12 0.8 1.2 1.6 2 2.4 i , drain current (a) drain-source on-resistance v = 6v gs d r , normalized ds(on) 9.0v 10v 7.0v 8.0v 0 2 4 6 8 10 12 0 1 2 3 4 5 i , drain current (a) drain-source on-resistance d r , normalized ds(on) v =10 v gs t = 125c j 25c -55c typical electrical characteristics figure 1. on-region characteristics. figure 2. on-resistance variation wit h gate voltage and drain current. figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with drain current and temperature. figure 5. transfer characteristics. figure 6. gate threshold variation with temperature. 2 4 6 8 10 0 2 4 6 8 10 12 v , gate to source voltage (v) i , drain current (a) 25 125 v = 10v ds gs d t = -55c j
nds9959.sam -50 -25 0 25 50 75 100 125 150 0.85 0.9 0.95 1 1.05 1.1 t , junction temperature (c) drain-source breakdown voltage (v) i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 1.4 0.001 0.003 0.01 0.03 0.1 0.3 1 3 10 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v =0v gs sd s 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 q , gate charge (nc) v , gate-source voltage (v) g gs i = 1.3a d v = 10v ds 20v 40v 0.1 0.2 0.5 1 2 5 10 20 50 10 20 50 100 200 400 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss g d s v dd r l v v in out v gs dut r gen 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t inverted 10% pulse width figure 7. breakdown voltage variation with temperature. figure 8. body diode forward voltage variation with current and temperature figure 9. capacitance characteristics. figure 10. gate charge characteristics. figure 11. switching test circuit figure 12. switching waveforms typical electrical characteristics (continued)
nds9959.sam 0.1 0.2 0.5 1 2 5 10 20 50 100 0.01 0.05 0.1 0.5 1 5 10 20 v , drain-source voltage (v) i , drain current (a) ds d v = 10v single pulse t = 25c gs a 1s 100ms dc 10ms rds(on) limit figure 13. transconductance variation with drain current. figure 14. maximum safe operating area. typical electrical characteristics (continued) 0 1 2 3 4 5 6 0 1 2 3 4 i , drain current (a) g , transconductance (siemens) t = -55c j d fs v = 15v ds 125c 25c 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 15 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
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